Performance-Driven Interconnect Global Routing - VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on

In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacity constraints as well as achieving higher routability and good routing flexibility. The init i a l solution consists of nets routed independently b y the SERT-C algorithm which minimizes the Elmore delay at critical sink of a Steiner tree. Then, al l the nets with the most congested edge , i.e., the edge with maximum flow, are ripped up and rerouted b y using an iterative hierarchical approach. For each iteration, a window is specified according to the span of the ripped-up nets or an upper bound i f the span is too large. Rerouting is done hierarchically within the window b y using integer programming t o optimize the flow uniformity. The aigorithm terminates when the flow uniformity can not be further improved. The algorithm has been implemented and interfaced with a placement tool. Experiments show that the algorithm can improve the flow uniformity b y 19% to 97%. The final results include the number of routing layers needed t o complete the routing. Thus, the method is also useful in determining the requii-ed number of layers for packaging design using multi-chip mode Is.